UniPro Power Estimation Model

For 65 nm and smaller CMOS processes, low power is the key challenge for next generation embedded platforms design. The necessary transition from single core or dual-core to heterogeneous multi-core SoC and Networks-on-Chip (NoC) makes the power efficient desings even more complex. For power efficient desings, power aspects should be taken into account throughout the whole design flow in embedded platforms, while modern design tools cover only the final stages. To achieve significant improvements in power efficiency at the system level, the design flow must incorporate new models and methodologies for power analysis of the whole architecture (including hardware and software solutions), new power efficient protocols, power-efficient parallel software programming and scheduling methodologies and this on the earlier stages of system development. On the other hand, drastic improvements in NoC power estimation could be gained by deep insight in computational models and in techniques used in power efficiency architecture, but also by developing a tailored simulator for embedded NoC at the behavioral level. The main idea of this project is to analyze power efficiency of computation models and protocols in embedded networked architecture. For this purpose, UniPro, its reference architecture and SystemC model will be taken as basis. A framework for power estimation will be developed and added to the exiting UniPro SystemC models, giving the possibility to the designers to get simulated power statistic of the network on the fly and as accurate as possible. The project will be done in 2 phases: the first to address the short-term, while the second will address the long-term targets. The first phase is expected to last about 6-12 months and focus primary on the corresponding theoretical investigation. The second phase will use the theoretical findings of the first phase to develop and implement solutions for the identified problems in MPSoC and NoC design.